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1 ltc3720 3720f single phase vrm8.5 current mode step-down controller n 5-bit programmable output voltage: 1.05v to 1.825v (vrm8.5) n no sense resistor required n 2% to 87% duty cycle at 200khz n t on(min) 100ns n supports active voltage positioning n true current mode control n stable with ceramic c out n dual n-channel mosfet synchronous drive n power good output voltage monitor n wide v in range: 4v to 36v n 1% 0.8v reference n adjustable current limit n adjustable switching frequency n forced continuous control pin n programmable soft-start n output overvoltage protection n optional short-circuit shutdown timer n micropower shutdown: i q < 30 m a n available in 28-lead narrow ssop package n power supplies for pentium ? processors n notebook computers and servers the ltc ? 3720 is a synchronous step-down switching regulator controller for cpu power. an output voltage between 1.05v and 1.825v is selected by a 5-bit code (intel vrm8.5 vid specification). the controller uses a valley current control architecture to deliver very low duty cycles without requiring a sense resistor. operating fre- quency is selected by an external resistor and is compen- sated for variations in v in and v out . discontinuous mode operation provides high efficiency operation at light loads. a forced continuous control pin reduces noise and rf interference and can assist second- ary winding regulation by disabling discontinuous mode operation when the main output is lightly loaded. fault protection is provided by internal foldback current limiting, an output overvoltage comparator and optional short-circuit shutdown timer. soft-start capability for sup- ply sequencing is accomplished using an external timing capacitor. the regulator current limit level is also user programmable. wide supply range allows operation from 4v to 36v at the input. , ltc and lt are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. pentium is a registered trademark of intel corporation. cmdsh-3 ups840 c out : cornell dubilier esre271m02b l1: sumida cep125-iromc l1 1 h 4.7 f 10 f 5 v in 5v to 24v v out 1.05v to 1.825v 20a + c out 270 f 2v 4 irf7811w 3 3720 f01a irf7811w 2 330k 0.1 f i on pgood v in tg sw boost run/ss i th sgnd intv cc bg pgnd 5-bit vid v osense vid0 vid1 vid2 vid3 vid4 0.33 f 20k ltc3720 470pf sense? sense + v cc + figure 1. high efficiency step-down converter output current (a) 0.01 efficiency (%) 100 3720 f01b 0.1 1 10 100 95 90 85 80 75 70 65 60 55 v in = 5v v in = 15v v out = 1.45v l1 = 1 h efficiency vs output current descriptio u features applicatio s u typical applicatio u
2 ltc3720 3720f (note 1) input supply voltage v in , i on ..................................................36v to C 0.3v boosted topside driver supply voltage boost .................................................. 42v to C 0.3v sw, sense + voltages ................................. 36v to C 5v extv cc , (boost C sw), run/ss, v cc vid0-vid4, pgood voltages ..................... 7v to C 0.3v fcb, v on , v rng voltages .......... intv cc + 0.3v to C 0.3v i th , v fb , v osense voltages ....................... 2.7v to C 0.3v tg, bg, intv cc , extv cc peak currents .................... 2a tg, bg, intv cc , extv cc rms currents .............. 50ma operating ambient temperature range ltc3720egn (note 2) ........................ C 40 c to 85 c junction temperature (note 3) ............................ 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ltc3720egn t jmax = 125 c, q ja = 95 c/ w the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 15v unless otherwise noted. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead narrow plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss v on pgood v rng fcb i th sgnd i on v fb sgnd v fb v osense vid0 vid1 boost tg sw sense + sense pgnd bg intv cc v in extv cc v cc vid4 vid3 vid2 symbol parameter conditions min typ max units main control loop i q input dc supply current normal 900 2000 m a shutdown supply current 15 30 m a v fb feedback reference voltage i th = 1.2v (note 4) l 0.792 0.800 0.808 v d v fb(linereg) feedback voltage line regulation v in = 4v to 30v, i th = 1.2v (note 4) 0.002 %/v d v fb(loadreg) feedback voltage load regulation i th = 0.5v to 1.9v (note 4) l C 0.05 C 0.3 % i fb feedback pin input current C5 50 na g m(ea) error amplifier transconductance i th = 1.2v (note 4) 1.4 1.7 2 ms v fcb forced continuous threshold l 0.76 0.8 0.84 v i fcb forced continuous pin current v fcb = 0.8v C 1 C 2 m a t on on-time i on = 60 m a, v on = 1.5v 200 250 300 ns i on = 30 m a, v on = 1.5v 425 500 575 ns t on(min) minimum on-time i on = 180 m a, v on = 0v 50 100 ns t off(min) minimum off-time i on = 60 m a, v on = 1.5v 250 400 ns v sense(max) maximum current sense threshold v rng = 1v, v fb = 0.76v l 113 133 153 mv v sense C C v sense + v rng = 0v, v fb = 0.76v l 79 93 107 mv v rng = intv cc , v fb = 0.76v l 158 186 214 mv v sense(min) minimum current sense threshold v rng = 1v, v fb = 0.84v C 67 mv v sense C C v sense + v rng = 0v, v fb = 0.84v C 47 mv v rng = intv cc , v fb = 0.84v C 93 mv d v fb(ov) output overvoltage fault threshold 5.5 7.5 9.5 % v fb(uv) output undervoltage fault threshold 520 600 680 mv v run/ss(on) run pin start threshold l 0.8 1.5 2 v
3 ltc3720 3720f the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 15v unless otherwise noted. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc3720e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d as follows: ltc3720egn: t j = t a + (p d ? 95 c/w) note 4: the ltc3720 is tested in a feedback loop that adjusts v fb to achieve a specified error amplifier output voltage (i th ). note 5: the ltc3720 vid dac is tested in a feedback loop that adjusts v osense to achieve a specified feedback voltage (v fb = 0.8v) for each dac vid code. note 6: each built-in pull-up resistor attached to vid inputs also has a series diode connected to v cc to allow input voltages higher than the v cc supply without damage or clamping. (see operation section for further details.) note 7: supply current is specified with all vid inputs floating. due to the internal pull-ups on the vid pins, the supply current will increase depending on the number of grounded vid lines. each grounded vid line will draw approximately (v cc C 0.6v)/40k ma. (see operation section for further details.) symbol parameter conditions min typ max units v run/ss(le) run pin latchoff enable threshold run/ss pin rising 4 4.5 v v run/ss(lt) run pin latchoff threshold run/ss pin falling 3.5 v i run/ss(c) soft-start charge current C 0.5 C 1.2 C 3 m a i run/ss(d) soft-start discharge current 0.8 1.8 3 m a v in (uvlo) undervoltage lockout v in falling l 3.4 3.9 v v in rising l 3.5 4.0 v tg r up tg driver pull-up on resistance tg high 2 3 w tg r down tg driver pull-down on resistance tg low 2 3 w bg r up bg driver pull-up on resistance bg high 3 4 w bg r down bg driver pull-down on resistance bg low 1 2 w tg t r tg rise time c load = 3300pf 20 ns tg t f tg fall time c load = 3300pf 20 ns bg t r bg rise time c load = 3300pf 20 ns bg t f bg fall time c load = 3300pf 20 ns internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v l 4.7 5 5.3 v d v ldo(loadreg) internal v cc load regulation i cc = 0ma to 20ma, v extvcc = 4v C 0.1 2% v extvcc extv cc switchover voltage i cc = 20ma, v extvcc rising l 4.5 4.7 v d v extvcc extv cc switch drop voltage i cc = 20ma, v extvcc = 5v 150 300 mv d v extvcc(hys) extv cc switchover hysteresis 200 mv pgood output d v fbh pgood upper threshold v fb rising 5.5 7.5 9.5 % d v fbl pgood lower threshold v fb falling C 5.5 C 7.5 C 9.5 % d v fb(hys) pgood hysteresis v fb returning 1 2 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v vid dac v cc operating supply voltage range 3.1 5.5 v v vid(t) vid0-vid4 logic threshold voltage v cc = 3.3v 0.4 1.2 2 v v vid(leak) vid0-vid4 leakage current v vid0 -v vid4 = v cc 0.01 1 m a d v osense dac output accuracy v osense programmed from C 0.25 0 0.25 % 1.05v to 1.825v (note 5), v cc = 5v r pullup pull-up resistance on vid v diode = 0.6v (note 6) 28 40 56 k w r vid resistance from v osense to v fb 61014 k w i vcc supply current (note 7) 1 10 m a
4 ltc3720 3720f typical perfor a ce characteristics uw current sense threshold vs i th voltage i th voltage (v) 0 200 current sense threshold (mv) 100 0 100 200 300 0.5 1.0 1.5 2.0 3720 g01 2.5 3.0 v rng = 1v 0.7v 0.5v 1.4v 2v i on current ( a) 1 10 on-time (ns) 100 1k 10k 10 100 3720 g02 v von = 0v v on voltage (v) 0 on-time (ns) 400 600 3720 g02 200 0 1 2 3 1000 i ion = 30 a 800 on-time vs i on current on-time vs v on voltage on-time vs temperature temperature ( c) ?0 on-time (ns) 200 250 300 25 75 3720 g04 150 100 ?5 0 50 100 125 50 0 i ion = 30 a v von = 0v v fb (v) 0 0 maximum current sense threshold (mv) 25 50 75 100 125 150 v rng = 1v 0.2 0.4 0.6 0.8 3720 g05 current limit foldback v rng voltage (v) 0.5 0 maximum current sense threshold (mv) 50 100 150 200 300 0.75 1.0 1.25 1.5 3720 g06 1.75 2.0 250 maximum current sense threshold vs v rng voltage maximum current sense threshold vs run/ss voltage run/ss voltage (v) 1.5 0 maximum current sense threshold (mv) 25 50 75 100 125 150 v rng = 1v 2 2.5 3 3.5 3729 g07 maximum current sense threshold vs temperature temperature ( c) 50 ?5 100 maximum current sense threshold (mv) 120 150 0 50 75 3720 g08 110 140 130 25 100 125 v rng = 1v temperature ( c) ?0 0.78 feedback reference voltage (v) 0.79 0.80 0.81 0.82 25 0 25 50 3720 g09 75 100 125 feedback reference voltage vs temperature
5 ltc3720 3720f typical perfor a ce characteristics uw error amplifier g m vs temperature extv cc switch resistance vs temperature run/ss latchoff thresholds vs temperature temperature ( c) 50 ?5 1.0 g m (ms) 1.4 2.0 0 50 75 3720 g10 1.2 1.8 1.6 25 100 125 input voltage (v) 0 input current ( a) shutdown current ( a) 800 1000 1200 15 25 3720 g11 600 400 510 20 30 35 200 0 30 40 60 50 20 10 0 extv cc open extv cc = 5v shutdown intv cc load current (ma) 0 ? intv cc (%) 0.2 0.1 0 40 3720 g12 0.3 0.4 0.5 10 20 30 50 input and shutdown currents vs input voltage intv cc load regulation temperature ( c) 50 ?5 0 extv cc switch resistance ( ) 4 10 0 50 75 3720 g13 2 8 6 25 100 125 temperature ( c) ?0 fcb pin current ( a) 0.50 0.25 0 25 75 3720 g14 0.75 1.00 ?5 0 50 100 125 1.25 1.50 temperature ( c) 50 ?5 ? fcb pin current ( a) 0 3 0 50 75 3720 g15 ? 2 1 25 100 125 pull-up current pull-down current fcb pin current vs temperature run/ss pin current vs temperature temperature ( c) ?0 3.0 run/ss threshold (v) 3.5 4.0 4.5 5.0 25 0 25 50 3720 g16 75 100 125 latchoff enable latchoff threshold temperature (c) ?0 2.0 undervoltage lockout threshold (v) 2.5 3.0 3.5 4.0 25 0 25 50 3720 g17 75 100 125 undervoltage lockout threshold vs temperature
6 ltc3720 3720f uu u pi fu ctio s run/ss (pin 1): run control and soft-start input. a capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/ m f) and the time delay for overcurrent latchoff (see applications information). forcing this pin below 0.8v shuts down the device. v on (pin 2): on-time voltage input. voltage trip point for the on-time comparator. tying this pin to the output voltage makes the on-time proportional to v out . the comparator input defaults to 0.7v when the pin is grounded, 2.4v when the pin is tied to intv cc . pgood (pin 3): power good output. open drain logic output that is pulled to ground when the output voltage is not within 7.5% of the regulation point. v rng (pin 4): sense voltage range input. the voltage at this pin is ten times the nominal sense voltage at maxi- mum output current and can be set from 0.5v to 2v by a resistive divider from intv cc . the nominal sense voltage defaults to 70mv when this pin is tied to ground, 140mv when tied to intv cc . fcb (pin 5): forced continuous input. tie this pin to ground to force continuous synchronous operation at low load or to intv cc to enable discontinuous mode operation at low load. i th (pin 6): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.8v corresponding to zero sense voltage (zero current). sgnd (pin 7, 10): signal ground. all small-signal compo- nents and compensation components should connect to this ground, which in turn connects to pgnd at one point. i on (pin 8): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thereby set the switching frequency. v fb (pin 9, 11): error amplifier feedback input. this pin connects to both the error amplifier input and to the output of the internal resistive divider. it can be used to attach additional compensation components if desired. v osense (pin 12): output voltage sense. the output voltage connects here to the input of the internal resistive feedback divider. vid0-vid4 (pins 13, 14, 15, 16, 17): vid digital inputs. the voltage identification (vid) code sets the internal feedback resistor divider ratio for different output voltages as shown in table 1. if unconnected, the pins are pulled high by internal 40k pull-up resistors. typical perfor a ce characteristics uw v out 50mv/div i l 10a/div 20 m s/div 3720 g18 load step = 0a to 15a v in = 15v v out = 1.5v fcb = 0v figure 7 circuit transient response (discontinuous mode) 20 m s/div 3720 g19 load step = 1a to 15a v in = 15v v out = 1.5v fcb = intv cc figure 7 circuit v out 50mv/div i l 10a/div transient response (forced continuous mode)
7 ltc3720 3720f v cc (pin 18): power supply voltage for vid. range is from 3.1v to 5.5v. extv cc (pin 19): external v cc input. when extv cc ex- ceeds 4.7v, an internal switch connects this pin to intv cc and shuts down the internal regulator so that controller and gate drive power is drawn from extv cc . do not exceed 7v at this pin and ensure that extv cc < v in . v in (pin 20): main input supply. decouple this pin to pgnd with an rc filter (1 w , 0.1 m f). intv cc (pin 21): internal 5v regulator output. the driver and control circuits are powered from this voltage. de- couple this pin to power ground with a minimum of 4.7 m f low esr tantalum capacitor. bg (pin 22): bottom gate drive. drives the gate of the bottom n-channel mosfet between ground and intv cc . pgnd (pin 23): power ground. connect this pin closely to the source of the bottom n-channel mosfet, the (C) terminal of c vcc and the (C) terminal of c in . sense C (pin 24): current sense comparator input. the (C) input is normally connected to pgnd. sense + (pin 25): current sense comparator input. the (+) input to the current comparator is normally connected to the sw node unless using a sense resistor (see appli- cations information). sw (pin 26): switch node. the (C) terminal of the boot- strap capacitor c b connects here. this pin swings from a diode voltage drop below ground up to v in . tg (pin 27): top gate drive. drives the top n-channel mosfet with a voltage swing equal to intv cc superim- posed on the switch node voltage sw. boost (pin 28): boosted floating driver supply. the (+) terminal of the bootstrap capacitor c b connects here. this pin swings from a diode voltage drop below intv cc up to v in + intv cc . uu u pi fu ctio s
8 ltc3720 3720f fu ctio al diagra u u w 1.4v 0.7v v rng 4 + + + + + + 2 2.4v v on 8 i on 5 fcb 19 extv cc 20 v in 1 a r on ost 0.7v v von i ion t on = (10pf) r sq 20k i cmp i rev q6 1v 3.3 a i thb shdn switch logic bg on fcnt f 0.8v + 4.7v ov 1 240k q1 q2 q3 0.8v 0.6v 0.6v i th r c c c1 ea ss 0.8v q4 + + 4 q5 6 run/ss c ss 1 3711 fd r1 v fb v fb vid4 17 v cc 18 vid3 16 vid2 15 vid1 14 vid0 40k 5 (all vid pins) v cc 13 12 run shdn 22 pgnd 23 sense pgood v osense 3 24 intv cc 21 sense + 25 sw 26 tg c b v in c in 27 boost 28 + + uv 0.74v r2 10k ov 0.86v 1.2 a 6v c vcc d b m2 m1 l1 c out vid dac + + 0.8v ref 5v reg 7 1 9 11 sgnd sgnd 10
9 ltc3720 3720f operatio u main control loop the ltc3720 is a current mode controller for dc/dc step-down converters. in normal operation, the top mosfet is turned on for a fixed interval determined by a one-shot timer ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current com- parator i cmp trips, restarting the one-shot timer and initiating the next cycle. inductor current is determined by sensing the voltage between the sense C and sense + pins using either the bottom mosfet on-resistance or a separate sense resistor. the voltage on the i th pin sets the comparator threshold corresponding to inductor valley current. the error amplifier ea adjusts this voltage by comparing the feedback signal v fb from the output voltage with an internal 0.8v reference. the feedback voltage is derived from the output voltage by a resistive divider dac that is set by the vid code pins vid0-vid4. if the load current increases, it causes a drop in the feedback voltage relative to the reference. the i th voltage then rises until the average inductor current again matches the load current. at low load currents, the inductor current can drop to zero and become negative. this is detected by current reversal comparator i rev which then shuts off m2, resulting in discontinuous operation. both switches will remain off with the output capacitor supplying the load current until the i th voltage rises above the zero current level (0.8v) to initiate another cycle. discontinuous mode operation is disabled by comparator f when the fcb pin is brought below 0.8v, forcing continuous synchronous operation. the operating frequency is determined implicitly by the top mosfet on-time and the duty cycle required to maintain regulation. the one-shot timer generates an on- time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in v in and v out . the nominal frequency can be adjusted with an external resistor r on . overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback voltage exits a 7.5% window around the regulation point. furthermore, in an overvoltage condition, m1 is turned off and m2 is turned on and held on until the overvoltage condition clears. foldback current limiting is provided if the output is shorted to ground. as v fb drops, the buffered current threshold voltage i thb is pulled down by clamp q3 to a 1v level set by q4 and q6. this reduces the inductor valley current level to one sixth of its maximum value as v fb approaches 0v. pulling the run/ss pin low forces the controller into its shutdown state, turning off both m1 and m2. releasing the pin allows an internal 1.2 m a current source to charge up an external soft-start capacitor c ss . when this voltage reaches 1.5v, the controller turns on and begins switch- ing, but with the i th voltage clamped at approximately 0.6v below the run/ss voltage. as c ss continues to charge, the soft-start current limit is removed. intv cc /extv cc power power for the top and bottom mosfet drivers and most of the internal controller circuitry is derived from the intv cc pin. the top mosfet driver is powered from a floating bootstrap capacitor c b . this capacitor is re- charged from intv cc through an external schottky diode d b when the top mosfet is turned off. when the extv cc pin is grounded, an internal 5v low dropout regulator supplies the intv cc power from v in . if extv cc rises above 4.7v, the internal regulator is turned off, and an internal switch connects extv cc to intv cc . this allows a high efficiency source connected to extv cc , such as an external 5v supply or a secondary output from the converter, to provide the intv cc power. voltages up to 7v can be applied to extv cc for additional gate drive. if the input voltage is low and intv cc drops below 3.5v, undervoltage lockout circuitry prevents the power switches from turning on. (refer to functional diagram)
10 ltc3720 3720f applicatio s i for atio wu uu the basic ltc3720 application circuit is shown in figure 1. external component selection is primarily de- termined by the maximum load current and begins with the selection of the sense resistance and power mosfet switches. the ltc3720 can use either a sense resistor or the on-resistance of the synchronous power mosfet for determining the inductor current. the desired amount of ripple current and operating frequency largely deter- mines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specification. maximum sense voltage and v rng pin inductor current is determined by measuring the voltage across a sense resistance that appears between the sense C and sense + pins. the maximum sense voltage is set by the voltage applied to the v rng pin and is equal to approximately (0.133)v rng . the current mode control loop will not allow the inductor current valleys to exceed (0.133)v rng /r sense . in practice, one should allow some margin for variations in the ltc3720 and external compo- nent values and a good guide for selecting the sense resistance is: r v i sense rng out max = 10 () an external resistive divider from intv cc can be used to set the voltage of the v rng pin between 0.5v and 2v resulting in nominal sense voltages of 50mv to 200mv. additionally, the v rng pin can be tied to sgnd or intv cc in which case the nominal sense voltage defaults to 70mv or 140mv, respectively. the maximum allowed sense voltage is about 1.33 times this nominal value. connecting the sense + and sense C pins the ltc3720 can be used with or without a sense resistor. when using a sense resistor, it is placed between the source of the bottom mosfet m2 and ground. connect the sense + pin to the source of the bottom mosfet and the sense C pin to pgnd so that the resistor appears between the sense + and sense C pins. kelvin connec- tions at the sense resistor ensure accurate current sens- ing. using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. alternatively, one can eliminate the sense resistor and use the bottom mosfet as the current sense element by simply connect- ing the se nse + pin to the switch node sw at the drain of the bottom mosfet and keep sense C connected to pgnd . this improves efficiency, but one must carefully choose the mosfet on-resistance as discussed below. power mosfet selection the ltc3720 requires two external n-channel power mosfets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage v (br)dss , threshold voltage v (gs)th , on-resistance r ds(on) , reverse transfer capacitance c rss and maximum current i ds(max) . the gate drive voltage is set by the 5v intv cc supply. consequently, logic-level threshold mosfets must be used in ltc3720 applications. if the input voltage is expected to drop below 5v, then sub-logic level threshold mosfets should be considered. when the bottom mosfet is used as the current sense element, particular attention must be paid to its on- resistance. mosfet on-resistance is typically specified with a maximum value r ds(on)(max) at 25 c. in this case, additional margin is required to accommodate the rise in mosfet on-resistance with temperature: r r ds on max sense t ()( ) = r the r t term is a normalization factor (unity at 25 c) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/ c as shown in figure 2. for a maximum temperature of 100 c, using a value r t = 1.3 is reasonable. the power dissipated by the top and bottom mosfets strongly depends upon their respective duty cycles and
11 ltc3720 3720f applicatio s i for atio wu uu the load current. when the ltc3720 is operating in continuous mode, the duty cycles for the mosfets are: d v v d vv v top out in bot in out in = = the resulting power dissipation in the mosfets at maxi- mum output current are: p top = d top i out(max) 2 r t(top) r ds(on)(max) + k v in 2 i out(max) c rss f p bot = d bot i out(max) 2 r t(bot) r ds(on)(max) both mosfets have i 2 r losses and the top mosfet includes an additional term for transition losses, which are largest at high input voltages. the constant k = 1.7a C1 can be used to estimate the amount of transition loss. the bottom mosfet losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. operating frequency the choice of operating frequency is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. the operating frequency of ltc3720 applications is deter- mined implicitly by the one-shot timer that controls the on-time t on of the top mosfet switch. the on-time is set by the current into the i on pin and the voltage at the v on pin according to: t v i pf on von ion = () 10 tying a resistor r on from v in to the i on pin yields an on- time inversely proportional to v in . for a step-down con- verter, this results in approximately constant frequency operation as the input supply varies: f v vr pf hz out von on = [] () 10 to hold frequency constant during output voltage changes, tie the v on pin to v out . the v on pin has internal clamps that limit its input to the one-shot timer. if the pin is tied below 0.7v, the input to the one-shot is clamped at 0.7v. similarly, if the pin is tied above 2.4v, the input is clamped at 2.4v. because the voltage at the i on pin is about 0.7v, the current into this pin is not exactly inversely proportional to v in , especially in applications with lower input voltages. to correct for this error, an additional resistor r on2 connected from the i on pin to the 5v intv cc supply will further stabilize the frequency. r v v r on on 2 5 07 = . changes in the load current magnitude will also cause frequency shift. parasitic resistance in the mosfet switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. by lengthening the on-time slightly as current increases, constant frequency operation can be maintained. this is accomplished with a resistive divider from the i th pin to the v on pin and v out . the values required will depend on the parasitic resistances in the specific application. a good starting point is to feed about 25% of the voltage change at the i th pin to the v on pin as junction temperature ( c) ?0 r t normalized on-resistance 1.0 1.5 150 3720 f02 0.5 0 0 50 100 2.0 figure 2. r ds(on) vs. temperature
12 ltc3720 3720f shown in figure 3a. place capacitance on the v on pin to filter out the i th variations at the switching frequency. the resistor load on i th reduces the dc gain of the error amp and degrades load regulation, which can be avoided by using the pnp emitter follower of figure 3b. inductor selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: d= ? ? ? ? - ? ? ? ? i v fl v v l out out in 1 lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l v fi v v out l max out in max = d ? ? ? ? - ? ? ? ? () () 1 once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m m ? cores. a variety of inductors designed for high current, low voltage applications are available from manu- facturers such as sumida, panasonic, coiltronics, coilcraft and toko. schottky diode d1 selection the schottky diode d1 shown in figure 1 conducts during the dead time between the conduction of the power mosfet switches. it is intended to prevent the body diode of the bottom mosfet from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. the diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. in order for the diode to be effective, the inductance between it and the bottom mosfet must be as small as possible, mandating that these components be placed adjacently. the diode can be omit- ted if the efficiency loss is tolerable. c in and c out selection the input capacitance c in is required to filter the square wave current at the drain of the top mosfet. use a low esr capacitor sized to handle the maximum rms current. ii v v v v rms out max out in in out @ () 1 applicatio s i for atio wu uu c von 0.01 f r von2 100k r von1 30k c c 3720 f03a v out r c v on i th ltc3720 c von 0.01 f r von2 10k q1 2n5087 r von1 3k 10k c c 3720 f03b v out intv cc r c v on i th ltc3720 (3a) figure 3. correcting frequency shift with load current changes (3b) kool m m is a registered trademark of magnetics, inc.
13 ltc3720 3720f this formula has a maximum at v in = 2v out , where i rms = i out(max) / 2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple d v out is approximately bounded by: dd + ? ? ? ? v i esr fc out l out 1 8 since d i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signifi- cant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. to dampen input voltage transients, add a small 5 m f to 50 m f aluminum electrolytic capacitor with an esr in the range of 0.5 w to 2 w . high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recom- mended to reduce the effect of their lead inductance. top mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications a 0.1 m f to 0.47 m f x5r or x7r dielectric capacitor is adequate. discontinuous mode operation and fcb pin the fcb pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin above its 0.8v threshold enables discontinuous operation where the bottom mosfet turns off when inductor current reverses. the load current at which current reverses and discontinuous operation begins de- pends on the amplitude of the inductor ripple current and will vary with changes in v in . tying the fcb pin below the 0.8v threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. in addition to providing a logic input to force continuous operation, the fcb pin provides a means to maintain a flyback winding output when the primary is operating in discontinuous mode. the secondary output v sec is nor- mally set as shown in figure 4 by the turns ratio n of the transformer. however, if the controller goes into discon- tinuous mode and halts switching due to a light primary load current, then v sec will droop. an external resistor divider from v sec to the fcb pin sets a minimum voltage v sec(min) below which continuous operation is forced until v sec has risen above its minimum. vv r r sec min () . =+ ? ? ? ? 08 1 4 3 applicatio s i for atio wu uu
14 ltc3720 3720f fault conditions: current limit and foldback the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the ltc3720, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i v r i limit sns max ds on t l =+d () () * r 1 2 the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs with the largest v in at the highest ambi- ent temperature, conditions that cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed mosfet junction temperature and the resulting value of i limit which heats the mosfet switches. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on- resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same amount below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. to further limit current in the event of a short circuit to ground, the ltc3720 includes foldback current limiting. if the output falls by more than 25%, then the maximum sense voltage is progressively lowered to about one sixth of its full value. minimum off-time and dropout operation the minimum off-time t off(min) is the smallest amount of time that the ltc3720 is capable of turning on the bottom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 350ns. the minimum off-time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: vv tt t in min out on off min on () () = + output voltage programming the output voltage is digitally set to levels between 1.05v and 1.825v using the voltage identification (vid) inputs vid0-vid4. an internal 5-bit dac configured as a preci- sion resistive voltage divider sets the output voltage in increments according to table 1. the vid codes are com- patible with intel vrm8.5 processor specifications. each vid input is pulled up by an internal 40k pull-up resistor from the intv cc supply and includes a series diode to prevent damage from vid inputs that exceed the supply. intv cc regulator an internal p-channel low dropout regulator produces the 5v supply that powers the drivers and internal circuitry within the ltc3720. the intv cc pin can supply up to 50ma rms and must be bypassed to ground with a minimum of 4.7 m f low esr capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers. applications using large mosfets with a high input voltage and high frequency of applicatio s i for atio wu uu *use r sense value if a sense resistor is connected between sense + and sense C . v in sense + ltc3720 sgnd fcb extv cc tg sw optional extv cc connection 5v < v sec < 7v r3 r4 3720 f04 t1 1:n bg pgnd + c sec 1 m f v out v sec v in + c in 1n4148 + c out figure 4. secondary output loop and extv cc connection
15 ltc3720 3720f operation may cause the ltc3720 to exceed its maximum junction temperature rating or rms current rating. most of the supply current drives the mosfet gates unless an external extv cc source is used. in continuous mode operation, this current is i gatechg = f(q g(top) + q g(bot) ). the junction temperature can be estimated from the equations given in note 3 of the electrical characteristics. for example, the ltc3720egn is limited to less than 19ma from a 30v supply: t j = 70 c + (19ma)(30v)(95 c/w) = 125 c for larger currents, consider using an external supply with the extv cc pin. extv cc connection the extv cc pin can be used to provide mosfet gate drive and control power from an external source during normal operation. whenever the extv cc pin is above 4.7v the internal 5v regulator is shut off and an internal 50ma p- channel switch connects the extv cc pin to intv cc . intv cc power is supplied from extv cc until this pin drops below 4.5v. do not apply more than 7v to the extv cc pin and ensure that extv cc v in . the following list summarizes the possible connections for extv cc : 1. extv cc grounded. intv cc is always powered from the internal 5v regulator. 2. extv cc connected to an external supply. a high effi- ciency supply compatible with the mosfet gate drive requirements (typically 5v) can improve overall efficiency. 3. extv cc connected to an output derived boost network. the low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7v. the system will start-up using the internal linear regulator until the boosted output supply is available. applicatio s i for atio wu uu table 1. vid output voltage programming vid4 vid3 vid2 vid1 vid0 v out (v) 00000 1.250v 00001 1.275v 00010 1.200v 00011 1.225v 00100 1.150v 00101 1.175v 00110 1.100v 00111 1.125v 01000 1.050v 01001 1.075v 01010 1.800v 01011 1.825v 01100 1.750v 01101 1.775v 01110 1.700v 01111 1.725v 10000 1.650v 10001 1.675v 10010 1.600v 10011 1.625v 10100 1.550v 10101 1.575v 10110 1.500v 10111 1.525v 11000 1.450v 11001 1.475v 11010 1.400v 11011 1.425v 11100 1.350v 11101 1.375v 11110 1.300v 11111 1.325v
16 ltc3720 3720f external gate drive buffers the ltc3720 drivers are adequate for driving up to about 60nc into mosfet switches with rms currents of 50ma. applications with larger mosfet switches or operating at higher frequencies requiring greater rms currents will benefit from using external gate drive buffers such as the ltc1693. alternately, the external buffer circuit shown in figure 5 can be used. note that the bipolar devices reduce the signal swing at the mosfet gate and benefit from an increased extv cc voltage of about 6v. applicatio s i for atio wu uu 3.3v or 5v run/ss v in intv cc run/ss d1 (6a) (6b) d2* c ss r ss * c ss *optional to override overcurrent latchoff r ss * 3720 f06 figure 6. run/ss pin interfacing with latchoff defeated back until the output reaches 75% of its final value. the pin can be driven from logic as shown in figure 6. diode d1 reduces the start delay while allowing c ss to charge up slowly for the soft-start function. after the controller has been started and given adequate time to charge up the output capacitor, c ss is used as a short-circuit timer. after the run/ss pin charges above 4v, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. a 1.8 m a cur- rent then begins discharging c ss . if the fault condition persists until the run/ss pin drops to 3.5v, then the con- troller turns off both power mosfets, shutting down the converter permanently. the run/ss pin must be actively pulled down to ground in order to restart operation. the overcurrent protection timer requires that the soft- start timing capacitor c ss be made large enough to guar- antee that the output is in regulation by the time c ss has reached the 4v threshold. in general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. a minimum soft-start capacitor can be estimated from: c ss > c out v out r sense (10 C4 [f/v s]) generally 0.1 m f is more than sufficient. overcurrent latchoff operation is not always needed or desired. load current is already limited during a short- circuit by the current foldback circuitry and latchoff figure 5. optional external gate driver q1 fmmt619 gate of m1 tg boost sw q2 fmmt720 q3 fmmt619 gate of m2 bg 10 3720 f05 intv cc pgnd q4 fmmt720 10 soft-start and latchoff with the run/ss pin the run/ss pin provides a means to shut down the ltc3720 as well as a timer for soft-start and overcurrent latchoff. pulling the run/ss pin below 0.8v puts the ltc3720 into a low quiescent current shutdown (i q < 30 m a). releasing the pin allows an internal 1.2 m a current source to charge up the external timing capacitor c ss . if run/ss has been pulled all the way to ground, there is a delay before starting of about: t v a csfc delay ss ss = m =m () 15 12 13 . . ./ when the voltage on run/ss reaches 1.5v, the ltc3720 begins operating with a clamp on i th of approximately 0.9v. as the run/ss voltage rises to 3v, the clamp on i th is raised until its full 2.4v range is available. this takes an additional 1.3s/ m f, during which the load current is folded
17 ltc3720 3720f operation can prove annoying during troubleshooting. the feature can be overridden by adding a pull-up current greater than 5 m a to the run/ss pin. the additional current prevents the discharge of c ss during a fault and also shortens the soft-start period. using a resistor to v in as shown in figure 6a is simple, but slightly increases shutdown current. connecting a resistor to intv cc as shown in figure 6b eliminates the additional shutdown current, but requires a diode to isolate c ss . any pull-up network must be able to pull run/ss above the 4.5v maximum threshold that arms the latchoff circuit and overcome the 4 m a maximum discharge current. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc3720 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the efficiency to drop at high output currents. in continuous mode the average output current flows through l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 w and r l = 0.005 w , the loss will range from 1% up to 10% as the output current varies from 1a to 10a for a 1.5v output. 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capaci- tance, among other factors. the loss is significant at input voltages above 20v and can be estimated from: transition loss @ (1.7a C1 ) v in 2 i out c rss f applicatio s i for atio wu uu 3. intv cc current. this is the sum of the mosfet driver and control currents. this loss can be reduced by supply- ing intv cc current through the extv cc pin from a high efficiency source, such as an output derived boost net- work or alternate supply if available. 4. c in loss. the input capacitor has the difficult job of filtering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. other losses, including c out esr loss, schottky diode d1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. if you make a change and the input current decreases, then the efficiency has increased. if there is no change in input current, then there is no change in efficiency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components shown in figure 7 will provide adequate compensation for most applications. for a detailed explanation of switching control loop theory see application note 76.
18 ltc3720 3720f design example as a design example, take a supply with the following specifications: v in = 7v to 24v (15v nominal), v out = 1.05v to 1.825v with typical at 1.5v, i out(max) = 15a, f = 300khz. first, calculate the timing resistor with v on = v out : r khz pf k on = ()() = 1 300 10 330 and choose the inductor for about 40% ripple current at the maximum v in : l v khz a v v h = ()()() - ? ? ? ? =m 15 300 0 4 15 1 15 24 08 . . . . selecting a standard value of 1 m h results in a maximum ripple current of: d= () m () ? ? ? ? = i v khz h v v a l 15 300 1 1 15 24 47 . . . next, choose the synchronous mosfet switch. because of the narrow duty cycle and large current, a single so-8 mosfet will have difficulty dissipating the power lost in the switch. choosing two irf7811a (r ds(on) = 0.013 w , c rss = 60pf, q ja = 50 c/w) yields a nominal sense voltage of: v sns(nom) = (15a)(0.5)(1.3)(0.012 w ) = 117mv tying v rng to intv cc will set the current sense voltage range for a nominal value of 140mv with current limit occurring at 186mv. to check if the current limit is acceptable, assume a junction temperature of about 100 c above a 50 c ambient with r 150 c = 1.6: applicatio s i for atio wu uu i mv aa limit 3 ()() w () + () = 186 05 16 0012 1 2 47 18 ... . and double check the assumed t j in the mosfet: p vv v a w bot = ? ? ? ? () w () = 24 1 5 24 21 7 2 16 0012 212 2 . . .. . t j = 50 c + (2.12w)(50 c/w) = 156 c because the top mosfet is on for such a short time, a single irf7811a will be sufficient. checking its power dissipation at current limit with r 90 c = 1.3: p v v a v a pf khz ww w bot = ()() w () + ()( )( )( )( ) =+= 15 24 21 7 1 3 0 012 1 7 24 21 7 60 300 046 038 084 2 2 . ... .. ... t j = 50 c + (0.84w)(50 c/w) = 92 c the junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. c in is chosen for an rms current rating of about 6a at temperature. the output capacitors are chosen for a low esr of 0.005 w to minimize output voltage changes due to inductor ripple current and load steps. the ripple voltage will be only: d v out(ripple) = d i l(max) (esr) = (4.7a) (0.005 w ) = 24mv
19 ltc3720 3720f however, a 0a to 15a load step will cause an output change of up to: d v out(step) = d i load (esr) = (15a) (0.005 w ) = 75mv the complete circuit is shown in figure 7. active voltage positioning active voltage positioning (also termed load deregula- tion or droop) describes a technique where the output voltage varies with load in a controlled manner. it is useful in applications where rapid load steps are the main cause of error in the output voltage. by positioning the output voltage above the regulation point at zero load, and below the regulation point at full load, one can use more of the applicatio s i for atio wu uu error budget for the load step. this allows one to reduce the number of output capacitors by relaxing the esr requirement. in the design example, figure 7, five 0.025 w capacitors are required in parallel to keep the output voltage within tolerance. using active voltage positioning, the same specification can be met with only three capacitors. in this case, the load step will cause an output voltage change of: d= () ? ? ? ? w () = va mv out step () . 15 1 3 0 025 125 figure 7. 15a cpu core voltage regulator at 300khz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss v on pgood v rng fcb i th sgnd i on v fb sgnd v fb v osense vid0 vid1 boost tg sw sense + sense pgnd bg intv cc v in extv cc v cc vid4 vid3 vid2 ltc3720 int v cc int v cc v in 330k 100k c ion 0.01 f r c 20k r f 10 c c2 100pf d b cmdsh-3 c c1 500pf c fb 100pf c2 6.8nf power good + v out 1.05v to 1.825v 15a v in 7v to 24v c out 270 f 2v 5 c in 10 f 50v 3 sgnd 3720 f07 c ss 0.1 f c b 0.33 f c f 0.1 f m1 irf7811a m2 irf7811a 2 4.7 f 6.3v ups840 l1 1 h 1
20 ltc3720 3720f applicatio s i for atio wu uu by positioning the output voltage 60mv above the regula- tion point at no load, it will only drop 65mv below the regulation point after the load step, well within the 100mv tolerance. implementing active voltage positioning requires setting a precise gain between the sensed current and the output voltage. because of the variability of mosfet on-resis- tance, it is prudent to use a sense resistor with active voltage positioning. in order to minimize power lost in this resistor, a low value is chosen of 0.003 w . the nominal sense voltage will now be: v sns(nom) = (0.003 w )(15a) = 45mv to maintain a reasonable current limit, the voltage on the v rng pin is reduced to its minimum value of 0.5v, corre- sponding to a 50mv nominal sense voltage. next, the gain of the ltc3720 error amplifier must be determined. the change in i th voltage for a corresponding change in the output current is: d= ? ? ? ? d = () w ()() = i v v ri av th rng sense out 12 24 0 003 15 1 08 .. the corresponding change in the output voltage is deter- mined by the gain of the error amplifier and feedback divider. the ltc3720 error amplifier has a transconduc- tance g m that is constant over both temperature and a wide 40mv input range. thus, by connecting a load resis- tance r vp to the i th pin, the error amplifier gain can be precisely set for accurate active voltage positioning. d= ? ? ? ? d igr v v v th m vp out out 08 . solving for this resistance value: r vi vg v vv vms mv k vp out th m out = d d == (. ) (. )(. ) (. )(. )( ) . 08 15 108 08 17 125 953 the gain setting resistance r vp is implemented with two resistors, r vp1 connected from i th to ground and r vp2 connected from i th to intv cc . the parallel combination of these resistors must equal r vp and their ratio determines nominal value of the i th pin voltage when the error amplifier input is zero. to center the load line around the regulation point, the i th pin voltage must be set to corre- spond to half the output current. the relation between i th voltage and the output current is: i v v ri i v v v aav v th nom rng sense out l () . . .... . = ? ? ? ? d ? ? ? ? + = ? ? ? ? w () ? ? ? ? + = 12 1 2 08 12 05 0 003 7 5 1 2 47 08 117 solving for the required values of the resistors: r v vi r v vv k k r v i r v v kk vp th nom vp vp th nom vp 1 2 5 5 5 5117 953 12 44 55 117 953 4073 == = === . . . . .. () ()
21 ltc3720 3720f applicatio s i for atio wu uu figure 8. 15a cpu core voltage regulator with active voltage positioning at 300khz figure 9. normal transient response (c out = 5 270 m f) v out 100mv/div 1.5v i l 10a/div c out = 5 270 m f20 m s/div 3720 f09 v in = 15v figure 7 circuit figure 10. transient response with active voltage positioning (c out = 3 270 m f) v out 100mv/div 1.5v i l 10a/div c out = 3 270 m f20 m s/div 3720 f10 v in = 15v figure 8 circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss v on pgood v rng fcb i th sgnd i on v fb sgnd v fb v osense vid0 vid1 boost tg sw sense + sense pgnd bg intv cc v in extv cc v cc vid4 vid3 vid2 ltc3720 int v cc int v cc v in 330k 100k c ion 0.01 f r vp2 40.2k r vp1 12.4k c ss 0.1pf c c 180pf c b 0.33 f c f 0.1 f power good + v out 1.05v to 1.825v 15a v in 5v to 24v c out 270 f 2v 3 c in 10 f 35v 3 sgnd 3720 f08 d b cmdsh-3 m1 irf7811a m2 irf7811a 2 4.7 f 6.3v ups840 r sense 0.003 r f 1 c fb 100pf r rng1 4.99k r rng2 45.3k l1 1 h + the modified circuit is shown in figure 8. figures 9 and 10 show the transient response without and with active voltage positioning. both circuits easily stay within 100mv of the 1.5v output. however, the circuit with active voltage positioning accomplishes this with only three output ca- pacitors rather than five. refer to linear technology design solutions 10 for additional information about active voltage positioning.
22 ltc3720 3720f figure 11. ltc3720 layout diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run/ss v on pgood v rng fcb i th sgnd i on v fb sgnd v fb v osense vid0 vid1 boost tg sw sense + sense pgnd bg intv cc v in extv cc v cc vid4 vid3 vid2 ltc3720 int v cc int v cc v in r on c ion r c r f 10 c ss c c1 c c2 c b c f d b power good + + v out v in c out c in sgnd l1 1 h d1 m1 m2 3720 f11 bold lines indicate high current paths pc board layout checklist when laying out the printed circuit board, use the follow- ing checklist to ensure proper operation of the controller. these items are also illustrated in figure 11. ? segregate the signal and power grounds. all small signal components should return to the sgnd pin at one point which is then tied to the pgnd pin close to the source of m2. ? place m2 as close to the controller as possible, keeping the sense C , bg and sense + traces short. ? connect the input capacitor(s) c in close to the power mosfets. this capacitor carries the mosfet ac current. minimize the loop area formed by c in , m1 and m2. applicatio s i for atio wu uu ? keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. ? connect the intv cc decoupling capacitor c vcc closely to the intv cc and pgnd pins. ? connect the top driver boost capacitor c b closely to the boost and sw pins. ? connect the v in pin decoupling capacitor c f closely to the v in and pgnd pins. ? vid0-vid4 interface circuitry must return to sgnd.
23 ltc3720 3720f u package descriptio gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) .386 ?.393* (9.804 ?9.982) gn28 (ssop) 0502 12 3 4 5 6 7 8 9 10 11 12 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 20 21 22 23 24 25 26 27 28 19 18 17 13 14 16 15 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .0075 ?.0098 (0.191 ?0.249) .053 ?.069 (1.351 ?1.748) .008 ?.012 (0.203 ?0.305) .004 ?.009 (0.102 ?0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 ltc3720 3720f ? linear technology corporation 2002 lt/tp 0203 2k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments ltc1628-pg dual, 2-phase synchronous step-down controller power good output, minimum input/output capacitors, 3.5v v in 36v ltc1628-sync dual, 2-phase synchronous step-down controller synchronizable 150khz to 300khz ltc1709-7/-8/-8.5/-9 2-phase synchronous step-down controllers up to 42a outputs, various vid tables, mobile, desktop, with 5-bit vid server, 3.5v v in 36v ltc1735 synchronous step-down controller burst mode tm operation, 16-pin narrow ssop, 3.5v v in 36v ltc1736 synchronous step-down controller with 5-bit vid mobile vid, 0.925v v out 2v, 3.5v v in 36v ltc1772 sot-23 step-down controller current mode, 550khz, very small solution size ltc1773 synchronous step-down controller up to 95% efficiency, 550khz, 2.65v v in 8.5v, 0.8v v out v in , synchronizable to 750khz ltc1778/ltc1778-1 no r sense synchronous step-down controllers no sense resistor required, 4v v in 36v, ltc3778 0.8v v out (0.9) v in ltc1876 2-phase, dual synchronous step-down controller with 2.6v v in 36v, power good output, 300khz operation step-up regulator ltc3701 dual, 2-phase step-down controller current mode,550khz, small 16-pin ssop, 2.5v v in < 9.8v ltc3711 5-bit adjustible, low duty cycle step-down controller 0.925v v out 2v, v in up to 36v, 24-pin gn ltc3728lx dual, 550khz, 2-phase synchronous step-down controllers phase lockable fixed frequency from 250khz to 550khz, ltc3728/ltc3728l 5mm 5mm qfn and ssop packages, small inductors and capacitors, integrated mosfet drivers ltc3730/ltc3732 3-phase synchronous dc/dc step-down controllers imvp iii and vrm 9.0/9.1 compliant, 600khz per phase, i out 60a, integrated mosfet drivers ltc3831 ddr memory termination power supply v out = 1/2 v in , i out up to 15a, 3v v in 8v, 700 m a supply current, 16-pin ssop package burst mode is registered trademark of linear technology corporation.

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